Leaping the Chasm to 7nm Semiconductor Design

Every new, smaller technology node developed in the semiconductor field has its own challenges, and the 7nm node is no exception. Usually a smaller technology node decreases price per transistor, but the cost benefits usually obtained from the smaller geometry are not as significant as in previous node changes. In fact, the increased complexity of lithography masks has made the unit cost per transistor slightly higher for 7nm devices. To offset these higher costs, products using 7nm semiconductors need higher margins, larger sales volumes and significantly higher performance than previous nodes. Achieving these goals requires designers to overcome a number of technical challenges, making upfront engineering simulation even more important than ever.7nm semiconductor design challenges

Upfront simulation enables engineers to detect and correct potential design problems early in the development process, when corrections are easy and inexpensive to make. Later on, once major features of the product are cemented in place, changes become costlier and more difficult. ANSYS solutions like ANSYS RedHawk and ANSYS SeaScape can help you with your upfront modeling, design, and analysis efforts.

Power noise closure is one of the major challenges at the 7nm semiconductor technology node. Because supply power can be as low as 470 mV with no change in the threshold voltage from previous nodes, the operating noise margin is significantly less for 7nm devices. As a result, design engineers need to investigate hundreds of scenarios involving variations in multiple parameters to develop a device that meets sign-off requirements. ANSYS RedHawk-SC can profile these hundreds of design combinations quickly to reduce development time.

Similarly, aging due to thermal and electromigration (EM) issues has become a challenge for 7nm devices. Thermal conductivity, limited by device architecture, and localized heating, due to higher metal densities at 7nm, can lead to higher device temperatures. This limits device lifetime and hurts performance. Using wider metal lines and more vias can increase EM violations. ANSYS RedHawk-CTA is a valuable thermal-aware statistical EM simulation tool for predicting these violations and eliminating them to meet sign-off requirements.

7nm semiconductor chip package thermal analysis

Accurate chip–package thermal analysis using ANSYS RedHawk-CTA

The customary siloed approach to solving these design problems is no longer feasible at 7nm. The interdependency of power noise on timing closure, and that of self-heating on EM, has increased at this node. ANSYS SeaScape, an analytics platform that was designed to handle big data, has the power and capacity to analyze data across siloes for faster, more efficient design closure.

To learn more about how ANSYS solutions can help you solve your 7nm semiconductor technology node challenges using upfront simulation, read the full article in the latest issue of ANSYS Advantage.


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