Achieving Power Noise Closure and Reliability Sign-off Accuracy for SoCs using Advanced Process Technologies

TSMC’s Partner of the Year Award

TSMC’s Partner of the Year Award

This year, ANSYS received yet another TSMC’s Partner of the Year Award in the category of joint development of the 10nm FinFET Design Infrastructure.  It has been 11 years since TSMC adopted ANSYS RedHawk as an integral part of its Reference Flow 5.0 in 2004, and that was the industry’s first reference flow to achieve dynamic power noise closure for nanometer designs.

Through longstanding, close collaboration between TSMC and ANSYS, ANSYS RedHawk and ANSYS Totem have always been enabled as power integrity and reliability solutions for the most advanced process technology. This has played and continues to play a critical role, enabling mutual customers to innovate and creating revolutionary electronic devices — for smart phones, high-performance computing, automotive, and wearable applications.

Why is foundry certification important for SoC design?

Reduced noise margins and higher voltage drop, typical for FinFET designs force designers to seek accurate analysis tools. When a foundry certifies an EDA tool for EM/IR sign-off, they thoroughly examine all the complex EM rules and carefully correlate the results against silicon measurement across thousands of test patterns and conditions. Hence, foundry certification is the ultimate emblem of accuracy. ANSYS tools, unlike other EM/IR tools have been the only certified solution for every process technology transition in the past 11 years. ANSYS RedHawk and Totem are the go-to solutions for sign-off.

As of today, there are 4 FinFET processes available for production: Intel 14nm, Samsung 14nm (14LPP), TSMC 16nm (16FFPLUS), and GlobalFoundries 14nm.  ANSYS RedHawk and Totem are the only EM/IR analysis solutions that are certified or qualified by all four of these foundries for their FinFET design platforms.

Our partnership with these leading foundries is beyond tool certification for static/dynamic power integrity and reliability. It has been extended into the realm of advanced methodology co-development, which includes but not limited to:

  • Self-heat and thermal reliability verification for sub-16nm FinFET designs
  • 3D-IC and Wafer Level Packaging (WLP) reliability verification
  • Chip-package-system ESD simulation and analysis.

ANSYS RedHawk and Totem have enabled 1000s of successful silicon tape-outs over these years. We continue to be the technology leader in this arena even today. The collaboration with these leading foundries for co-development, validation and sign-off certification of the ANSYS RedHawk and Totem for advanced process technologies (16/14nm, 10nm, and even 7nm), no doubt offers our bleeding edge customers the assurance against risk of silicon failure. This allows our mutual customers to design innovative, robust and reliable SoCs.


While the award is a nice token of recognition of the collaboration between a foundry and ANSYS, the real value is in the stream of on-going multi-faceted collaborative work that:

  • Enables the deployment of advanced process technologies for the foundry
  • Empowers customers to innovate and create robust and reliable SoCs with optimized power delivery networks (PDN)
  • Offers customers the best assurance against risk of silicon failure — as a result, cost-effective

To learn more about achieving power noise closure, I invite you to watch this on-demand webinar. And, please feel free to ask questions in the comments section below.