Power noise integrity challenges designers face in FinFET-based design
Recently, there has been a lot of talk around designing systems-on-chips (SoCs) using FinFET technology. So what is a FinFET and what’s all the noise about? Simply put, FinFET is a three-dimensional field-effect transistor (FET) where the gate is wrapped around an elevated channel, creating a “fin”. Compared to traditional planar MOS transistors, FinFET architecture offers reduced leakage power and increased drive current, resulting in lower power, higher performance SoCs for mobile, networking, computing, and other applications.
Leading manufacturers such as GlobalFoundries, Intel, Samsung and TSMC and their EDA partners are spending a lot of effort to support the new technology. Recent announcements by Samsung and GlobalFoundries expound upon their collaboration in delivering global capacity for 14 nanometer FinFET process technology. To make the transition to FinFET based designs as smooth as possible for the design community, EDA and IP vendors are working closely with foundries to ensure that the tools can support the associated complexities. For example, ANSYS power integrity and electromigration tools were recently certified by TSMC for 16nm FinFET technology.
FinFET based designs enable devices to operate at a lower supply voltage, reducing overall power while improving performance. However, this results in decreased power noise margins, further exacerbating the challenges associated with power budgeting, voltage drop, and overall power noise reliability sign-off. These tighter noise margins emphasize the need for an accurate analysis solution.
Another power noise challenge designers are facing is related to the higher drive strengths of FinFET devices as compared to planar devices. This results in sharper changes in current. When the higher di/dt combines with a resistive and inductive chip-package power delivery network (PDN), it spells trouble for power noise integrity.
Higher drive strength per unit area also means an increase in current density. Increased current flow through the same or smaller metal interconnects means greater EM risk. Today’s designs have much more stringent EM rules. Limits have a greater dependence on current direction, metal topology and via types. Poor heat escape paths for the fins result in greater localization of heat sources, further impacting EM and electrostatic discharge (ESD). In addition, the narrowing margin between the nominal voltages and device breakdown voltages is shrinking the design window that is available for ESD engineers, thus requiring systematic ESD checking during the design phase.
When it comes to power noise and reliability sign-off, reduced noise margins and higher voltage drop and reliability risks force designers to exercise tighter control over analysis accuracy. An accurate analysis requires accurate modeling of all the different elements that interplay during a switching event on a chip, including switching transistors, decoupling capacitors, interconnect gate capacitances, and on-chip, package and PCB interconnect parasitics (RLCK). In addition, today’s highly-integrated SoC’s have a large number of distinct power and ground supplies, each with hundreds of C4 bumps supplying current for a wide range of activity. The current profile can change significantly across the chip and over time. This increases the need for a holistic approach to analyzing the power delivery network. Chip and package PDN’s must be analyzed within the context of the chip-package system.
Unlike timing, power integrity is a global phenomenon as the PDN spans across the chip, package and the system. The challenge is to ensure that your analysis has maximum coverage — accounting for all aspects of die, package and system PDN power, noise, and reliability, while maintaining signoff accuracy.
As we scale technology nodes into 16 nm and below, the focus on power noise and reliability sign-off becomes a necessary requirement. Simulation solutions that have the capacity and modeling sophistication to enable ‘flat’ analysis while considering various on-chip and chip-package coupling mechanisms, as well as power noise impact on reliability such as EM and ESD, will ensure greater confidence in sign-off accuracy and coverage.
For more information on ANSYS solutions for electronics, visit our integrated circuits website page. To learn more about FinFET technology and its challenges, consider reading the following articles on Semiconductor Engineering:
- FinFET Based Designs: Power Analysis Considerations
- FinFET Reliability Issues
- ESD Signoff No Longer A “Nice to Have” In FinFET Design Era
- Power Noise And Reliability Sign-off For The Sub-20nm FinFET Era
- How Reliable Are Interconnects In 16nm FinFET Designs?
- Reliability Challenges In 16nm FinFET Design