Delivering a truly innovative product for the mobile revolution requires optimization at every level of design for power, performance, thermal and structural integrity. The success of today’s electronic products are tied to the success of their entire system, including all components from antenna to board, and from chip to chassis. Designing a smart watch, for example, requires multiple iterations of chip, package, board, antenna, and cooling strategy to arrive at a final optimized product.
A higher-than-expected power consumption at the chip level will result in shorter battery lifetimes and limited reliability. Likewise, a chip with a higher-than-expected thermal profile impacts product cost and performance if package changes are required.
Power, performance and cost are therefore key drivers in the race to design the next innovative mobile devices. The ANSYS chip package system flow enables designers to predict real-world performance of their products through simulation, giving them confidence in achieving first-time design success. ANSYS 17.0 adds significant advancements to its chip package system design flow to address design challenges in power integrity, signal integrity, ESD, thermal and structural challenges.
Enabling power efficient systems
Low power design means small voltage margins, fast transitions between power states, and low swing communication between components. These make systems more susceptible to failures, and therefore require signal and power integrity simulation considering all interactions between chip, package and board. Analyzing the signal integrity of a system requires co-simulation of IO ring, package, PCB decoupling and channel to ensure a system will meet its timing and performance target.
Likewise for power integrity analysis, co-simulation of the chip, package, and board are critical for optimizing the power delivery network (PDN) and implementation of low power design features. However, any power integrity solution must ensure product performance over all modes of operation. How can one achieve this in the case of a chip designed by another team, or even an external chip vendor?
Chip modeling for system optimization
Chip models provide key physical, electrical, and thermal information for system-level simulation, and can be generated from chip-level simulation tools for any mode of operation. ANSYS IC solutions like RedHawk and Totem validate low-power design techniques at the chip-level and also generate a Chip Power Model (CPM) for system-level PI/EMI analysis. In ANSYS 17.0, SIwave imports a CPM to drive a chip-package-board co-simulation, which can be used to optimize component placement and decoupling capacitor solutions to achieve performance and cost targets. Board designers using SIwave now have direct access to thermal simulation data that directly impacts their board through Joule heating, and can map these effects to their electrical analysis without the need to ‘learn’ additional CFD-based tools.
Achieving thermally sustainable performance
Thermal/structural integrity is another critical design consideration for packages/PCBs, as thermal gradients in the system translate into structural stress. Thermal impact on the package, especially from the IC, is a key driver for material selection, cooling, and form factor decisions, which ultimately determine the size, weight and cost of the final product. Therefore it is critical for package and system designers to accurately model the thermal signature of their system and the thermal stress on their product’s structural integrity. To enable this analysis, ANSYS chip package system flows use the same electrical layout database in thermal and mechanical analysis, so package designers can easily map thermal to structural analysis to highlight deformation, strain and stress issues on the package.
As different temperature signatures occur with different modes of operation, a Chip Thermal Model (CTM) can be imported into ANSYS thermal analysis in Icepak, to validate package performance over the range of chip operating conditions. The package designer can then experiment with material properties, layer thicknesses and boundary conditions to optimize their design for a specific chip and cooling solution.
Who will win the race to the next mobile device breakthrough?
As power, performance and cost are key drivers in the race to create the next innovative mobile devices, the ANSYS chip package system design flow enables designers to collaborate early in the design phase and achieve first-time design success. ANSYS 17.0 provides a unique virtual prototyping flow to simulate real-world electrical, thermal and mechanical behavior of a product, enabling design engineers to meet their system power and performance targets while reducing cost.
To learn more, register for the ANSYS 17.0 Webinar Series: 10x More Productivity for Chip Package System Workflows on March 1st.