Aveek Sarkar

About Aveek Sarkar

Aveek Sarkar is VP, Sales and Support, for the Semiconductor BU at ANSYS. He joined ANSYS through its acquisition of Apache Design Solutions where he was one of its earliest employees. He is responsible for all customer engagements for the Semiconductor Business Unit of ANSYS. While at Apache he had taken on different roles and responsibilities including his last role as Vice President of WW Customer Support and Product Engineering. He previously worked at Sun Microsystems on circuit design, power delivery and chip-package co-design for several generations of UltraSparc processors. Mr. Sarkar holds a B. Tech from the Indian Institute of Technology, Kanpur, a MSEE from Oregon State University, and MBA from Santa Clara University.

Creating Reliable SoC Designs Using N7 and InFO-WLP Technologies

According to Gartner, designing, testing and manufacturing 7nm FinFET-based system on a chip (SoC) requires massive resources: as much as $270 million and 500 man-years to bring the chip to market. Encapsulating such chips within a 2.5/3D package such as InFO-WLP improves power, performance and form factor while increasing the cost of design. To make a profit on that level of investment, the market for these chips tend to be high-end mobile and enterprise applications. To satisfy customer needs in these demanding markets, design teams have to deliver highly integrated devices that operate seamlessly and reliably for long periods of time. Additionally, you have to reduce the engineering time and cost, and ensure “first-time” working silicon. To do this you will need to move away from the traditional silo-based design flow to a chip-package-board co-simulation workflow and methodology. Continue reading

Introducing ANSYS SeaScape for Chip Simulation

seahawk seascapeDue to the volumes of data that need to be analyzed and the limits in simulation tool capabilities and processing power, sign-off in chip and electronic system design has traditionally followed a monolithic, margin-based approach that has resulted in larger die-size and longer development times. Today I’d like to tell you about a fundamentally new approach and software architecture called ANSYS SeaScape that will revolutionize chip simulation by harnessing the power of elastic computing, machine learning and big data to perform multiphysics simulations and design more compact, complex chips. This approach has demonstrated its ability speed up chip design and help eliminate many of the inefficiencies of traditional methodologies. Continue reading

EMI/EMC Induced Automotive System Failure

Mention of EMI/EMC-induced automotive system failure in the press last week coincided with one of the bigger technical conferences held annually in Silicon Valley – DesignCon. It was in this conference two years ago that we organized a workshop on chip–package–system simulation methodologies specifically as they pertain to EMI/EMC analysis.

Electromagnetic interference, coupling and susceptibility are complex topics. To predict such an event or occurrence requires design teams separated by organizational boundaries to collaborate effectively “outside” the silos they reside in. An automotive system design company working on the next-generation air-bag control system will be responsible for designing the printed circuit board (PCB) to meet stringent performance, reliability and cost metrics. Its teams typically perform numerous simulations to ensure that the board, by itself, meets the requirements outlined for the team. However, PCBs are passive electrically. They (along with the cables) radiate only when the integrated circuit (IC) that is present on these PCBs performs the necessary operations and generates current flow through the various traces. Continue reading