Every new, smaller technology node developed in the semiconductor field has its own challenges, and the 7nm node is no exception. Usually a smaller technology node decreases price per transistor, but the cost benefits usually obtained from the smaller geometry are not as significant as in previous node changes. In fact, the increased complexity of lithography masks has made the unit cost per transistor slightly higher for 7nm devices. To offset these higher costs, products using 7nm semiconductors need higher margins, larger sales volumes and significantly higher performance than previous nodes. Achieving these goals requires designers to overcome a number of technical challenges, making upfront engineering simulation even more important than ever.
Semiconductors touch every aspect of our lives — from the computers that we work on to the automobiles we drive to the medical devices that keep us healthy. As these amazing chips become smaller and more packed with functionality (the latest NVIDIA graphics chip has 21 billion transistors!), designing and producing them becomes far more complicated. Yet increased demand for smaller, more powerful integrated circuits is increasing so companies can create the products of the future. Continue reading
I’m happy to announce that our team will once again be showcasing our industry-leading solutions at the 54th Annual Design Automation Conference (#54DAC) in Austin, TX. I invite you to stop by and meet with our domain experts in booth 647, from June 19-21, to learn how our industry-leading technology can help meet your SoC design challenges with production-proven solutions. Continue reading
According to Gartner, designing, testing and manufacturing 7nm FinFET-based system on a chip (SoC) requires massive resources: as much as $270 million and 500 man-years to bring the chip to market. Encapsulating such chips within a 2.5/3D package such as InFO-WLP improves power, performance and form factor while increasing the cost of design. To make a profit on that level of investment, the market for these chips tend to be high-end mobile and enterprise applications. To satisfy customer needs in these demanding markets, design teams have to deliver highly integrated devices that operate seamlessly and reliably for long periods of time. Additionally, you have to reduce the engineering time and cost, and ensure “first-time” working silicon. To do this you will need to move away from the traditional silo-based design flow to a chip-package-board co-simulation workflow and methodology. Continue reading
An automobile is the biggest and most complex connected device used by consumers today. Advanced driver assistance systems (ADAS) is one of the fastest growing automotive applications. Stringent government requirements on automotive safety, fuel consumption and technology-focused consumer preferences are fueling the growth of ADAS. Driven primarily by safety, ADAS capabilities were first implemented in premium vehicles as key differentiators to enhance the user experience and protect the vehicle and its occupants. It started with features like parking assistance, adaptive breaking systems (ABS), adaptive cruise control and tire pressure monitoring. Continue reading
Due to the volumes of data that need to be analyzed and the limits in simulation tool capabilities and processing power, sign-off in chip and electronic system design has traditionally followed a monolithic, margin-based approach that has resulted in larger die-size and longer development times. Today I’d like to tell you about a fundamentally new approach and software architecture called ANSYS SeaScape that will revolutionize chip simulation by harnessing the power of elastic computing, machine learning and big data to perform multiphysics simulations and design more compact, complex chips. This approach has demonstrated its ability speed up chip design and help eliminate many of the inefficiencies of traditional methodologies. Continue reading
The electrification of our world continues at a rapid pace. Having established a strong footprint across the globe via communication technologies, the high tech industry is now forming alliances with automotive companies to make our cars smarter. You need look no further than the 2016 Consumer Electronics Show, where the automobile industry stole the show with their demonstrations of autonomous vehicles, which are moving ever closer to market. Continue reading
The internet has inspired the growth and permeation of electronics into everything from coffee machines to automobiles, hand‐held devices, mobile smart phones, healthcare monitoring and treatment equipment, communication devices, high‐end servers and more. Most of these are “always on,” and require the systems on chip (SoC) that drive the electronics to be: Continue reading
This year, ANSYS received yet another TSMC’s Partner of the Year Award in the category of joint development of the 10nm FinFET Design Infrastructure. It has been 11 years since TSMC adopted ANSYS RedHawk as an integral part of its Reference Flow 5.0 in 2004, and that was the industry’s first reference flow to achieve dynamic power noise closure for nanometer designs.
Through longstanding, close collaboration between TSMC and ANSYS, ANSYS RedHawk and ANSYS Totem have always been enabled as power integrity and reliability solutions for the most advanced process technology. This has played and continues to play a critical role, enabling mutual customers to innovate and creating revolutionary electronic devices — for smart phones, high-performance computing, automotive, and wearable applications. Continue reading
Modern high-tech products using chips that are designed with the latest deep sub-micron process technologies (28nm and below) and FinFET technology offer higher performance, smaller footprint and lower power. However, power integrity analysis and reliability challenges become increasingly complex for chip package designs using these devices.
More stringent manufacturing rules present basic layout challenges and new design innovations require careful consideration of effects such as electromigration (EM), electrostatic discharge (ESD) and noise coupling through substrate, signal and power rails. Even the most thorough sign-off process can often fail to prevent tape-out hurdles or extensive redesign. Therefore, forward-thinking design teams need to address reliability and power integrity long before final sign-off, accounting for their impact during the design process itself. Continue reading