Creating Reliable SoC Designs Using N7 and InFO-WLP Technologies

According to Gartner, designing, testing and manufacturing 7nm FinFET-based system on a chip (SoC) requires massive resources: as much as $270 million and 500 man-years to bring the chip to market. Encapsulating such chips within a 2.5/3D package such as InFO-WLP improves power, performance and form factor while increasing the cost of design. To make a profit on that level of investment, the market for these chips tend to be high-end mobile and enterprise applications. To satisfy customer needs in these demanding markets, design teams have to deliver highly integrated devices that operate seamlessly and reliably for long periods of time. Additionally, you have to reduce the engineering time and cost, and ensure “first-time” working silicon. To do this you will need to move away from the traditional silo-based design flow to a chip-package-board co-simulation workflow and methodology. Continue reading

Design of Advanced Driver Assistance Systems – A CPS Approach

An automobile is the biggest and most complex connected device used by consumers today. Advanced driver assistance systems (ADAS) is one of the fastest growing automotive applications. Stringent government requirements on automotive safety, fuel consumption and technology-focused consumer preferences are fueling the growth of ADAS. Driven primarily by safety, ADAS capabilities were first implemented in premium vehicles as key differentiators to enhance the user experience and protect the vehicle and its occupants. It started with features like parking assistance, adaptive breaking systems (ABS), adaptive cruise control and tire pressure monitoring. Continue reading

Introducing ANSYS SeaScape for Chip Simulation

seahawk seascapeDue to the volumes of data that need to be analyzed and the limits in simulation tool capabilities and processing power, sign-off in chip and electronic system design has traditionally followed a monolithic, margin-based approach that has resulted in larger die-size and longer development times. Today I’d like to tell you about a fundamentally new approach and software architecture called ANSYS SeaScape that will revolutionize chip simulation by harnessing the power of elastic computing, machine learning and big data to perform multiphysics simulations and design more compact, complex chips. This approach has demonstrated its ability speed up chip design and help eliminate many of the inefficiencies of traditional methodologies. Continue reading

Electrification – The Need for Optimizing Power, Performance and Cost

The electrification of our world continues at a rapid pace. Having established a strong footprint across the globe via communication technologies, the high tech industry is now forming alliances with automotive companies to make our cars smarter. You need look no further than the 2016 Consumer Electronics Show, where the automobile industry stole the show with their demonstrations of autonomous vehicles, which are moving ever closer to market. Continue reading

10X Gain in Productivity of Chip‐level Power Integrity Analysis

The internet has inspired the growth and permeation of electronics into everything from coffee machines to automobiles, hand‐held devices, mobile smart phones, healthcare monitoring and treatment equipment, communication devices, high‐end servers and more. Most of these are “always on,” and require the systems on chip (SoC) that drive the electronics to be: Continue reading

Achieving Power Noise Closure and Reliability Sign-off Accuracy for SoCs using Advanced Process Technologies

TSMC’s Partner of the Year Award

TSMC’s Partner of the Year Award

This year, ANSYS received yet another TSMC’s Partner of the Year Award in the category of joint development of the 10nm FinFET Design Infrastructure.  It has been 11 years since TSMC adopted ANSYS RedHawk as an integral part of its Reference Flow 5.0 in 2004, and that was the industry’s first reference flow to achieve dynamic power noise closure for nanometer designs.

Through longstanding, close collaboration between TSMC and ANSYS, ANSYS RedHawk and ANSYS Totem have always been enabled as power integrity and reliability solutions for the most advanced process technology. This has played and continues to play a critical role, enabling mutual customers to innovate and creating revolutionary electronic devices — for smart phones, high-performance computing, automotive, and wearable applications. Continue reading

How Is FinFET Technology Changing the Meaning of Chip Sign-Off?

Physical Representation FinFET TechnologyModern high-tech products using chips that are designed with the latest deep sub-micron process technologies (28nm and below) and FinFET technology offer higher performance, smaller footprint and lower power. However, power integrity analysis and reliability challenges become increasingly complex for chip package designs using these devices.

More stringent manufacturing rules present basic layout challenges and new design innovations require careful consideration of effects such as electromigration (EM), electrostatic discharge (ESD) and noise coupling through substrate, signal and power rails. Even the most thorough sign-off process can often fail to prevent tape-out hurdles or extensive redesign. Therefore, forward-thinking design teams need to address reliability and power integrity long before final sign-off, accounting for their impact during the design process itself. Continue reading

RedHawk 2014 Enables FinFET-Based Designs

image of ANSYS RedHawk GUIToday, I’m pleased to announce the launch of ANSYS Redhawk 2014. RedHawk was the industry’s first foundry-certified, full-chip sign-off solution for power noise and reliability. Over the past 10 years, its accuracy, performance and scalability benefits have enabled thousands of successful designs to make it into production by all major semiconductor companies. The newest version of the software will help to ensure that RedHawk continues to be a technology leader and solution of choice for chip designers around the world. Continue reading

What’s With All The Noise About FinFETs?

Power noise integrity challenges designers face in FinFET-based design

ReFinFET2cently, there has been a lot of talk around designing systems-on-chips (SoCs) using FinFET technology. So what is a FinFET and what’s all the noise about? Simply put, FinFET is a three-dimensional field-effect transistor (FET) where the gate is wrapped around an elevated channel, creating a “fin”. Compared to traditional planar MOS transistors, FinFET architecture offers reduced leakage power and increased drive current, resulting in lower power, higher performance SoCs for mobile, networking, computing, and other applications. Continue reading

Apache Design Acquisition Done Right

PrintTwo years ago, ANSYS, Inc. acquired Apache Design to broaden its presence in the IC-aware system simulation market, particularly for the high-growth mobile and consumer electronics segments. We had a vision of combining chip-level analysis and modeling solutions from Apache with package and systems electromagnetics, thermal/fluids and mechanical simulation platforms from ANSYS, to enable the next generation of low-power, energy-efficient products. We had also underscored our commitment toward customers’ success by providing continuous support and technology innovation. On our two-year anniversary, we reflect on the progress that we have made toward this vision.

Since the acquisition by ANSYS, Apache has achieved: Continue reading