Who doesn’t have power issues designing chips? Power management and power closure are primary concerns for system-on-chip (SoC) designs. So what is the best way to address these power challenges? By using simulation technologies from early in the IC design phase to accurately predict the chip’s power consumption and analyze its power delivery network integrity within the context of the full system.
To learn more, register to attend ANSYS subsidiary Apache’s technical webinar series for IC design, with presentations from leading semiconductor companies Nvidia, Freescale and GlobalFoundries. Featured at the most recent Design Automation Conference (DAC), these customers will share design challenges, power methodologies – and their results using Apache tools. Continue reading