Modern high-tech products using chips that are designed with the latest deep sub-micron process technologies (28nm and below) and FinFET technology offer higher performance, smaller footprint and lower power. However, power integrity analysis and reliability challenges become increasingly complex for chip package designs using these devices.
More stringent manufacturing rules present basic layout challenges and new design innovations require careful consideration of effects such as electromigration (EM), electrostatic discharge (ESD) and noise coupling through substrate, signal and power rails. Even the most thorough sign-off process can often fail to prevent tape-out hurdles or extensive redesign. Therefore, forward-thinking design teams need to address reliability and power integrity long before final sign-off, accounting for their impact during the design process itself. Continue reading
Today, I’m pleased to announce the launch of ANSYS Redhawk 2014. RedHawk was the industry’s first foundry-certified, full-chip sign-off solution for power noise and reliability. Over the past 10 years, its accuracy, performance and scalability benefits have enabled thousands of successful designs to make it into production by all major semiconductor companies. The newest version of the software will help to ensure that RedHawk continues to be a technology leader and solution of choice for chip designers around the world. Continue reading
Power noise integrity challenges designers face in FinFET-based design
Recently, there has been a lot of talk around designing systems-on-chips (SoCs) using FinFET technology. So what is a FinFET and what’s all the noise about? Simply put, FinFET is a three-dimensional field-effect transistor (FET) where the gate is wrapped around an elevated channel, creating a “fin”. Compared to traditional planar MOS transistors, FinFET architecture offers reduced leakage power and increased drive current, resulting in lower power, higher performance SoCs for mobile, networking, computing, and other applications. Continue reading
Two years ago, ANSYS, Inc. acquired Apache Design to broaden its presence in the IC-aware system simulation market, particularly for the high-growth mobile and consumer electronics segments. We had a vision of combining chip-level analysis and modeling solutions from Apache with package and systems electromagnetics, thermal/fluids and mechanical simulation platforms from ANSYS, to enable the next generation of low-power, energy-efficient products. We had also underscored our commitment toward customers’ success by providing continuous support and technology innovation. On our two-year anniversary, we reflect on the progress that we have made toward this vision.
Since the acquisition by ANSYS, Apache has achieved: Continue reading
Who doesn’t have power issues designing chips? Power management and power closure are primary concerns for system-on-chip (SoC) designs. So what is the best way to address these power challenges? By using simulation technologies from early in the IC design phase to accurately predict the chip’s power consumption and analyze its power delivery network integrity within the context of the full system.
To learn more, register to attend ANSYS subsidiary Apache’s technical webinar series for IC design, with presentations from leading semiconductor companies Nvidia, Freescale and GlobalFoundries. Featured at the most recent Design Automation Conference (DAC), these customers will share design challenges, power methodologies – and their results using Apache tools. Continue reading