Chip-Package-System Workflow Breaks Down the Barriers in Electronics Design

Chip-Package-System Workflow Engineers are challenged to design modern electronic systems that operate at higher speeds with lower power with ever greater functionality in an ever shrinking footprint. These design challenges drive engineers to perform Chip-Package-System (CPS) co-design and analysis. However, the design flow is often unconnected, and design data is exchanged manually leading to slow design times and error prone design methodologies. ANSYS 18 breaks down the barriers between simulation domains and delivers a Chip-Package-System workflow that enables engineers to accomplish their work in a rapid and convenient way.

The ANSYS Chip-Package-System (CPS) design flow supports end-to-end simulation of electronic systems comprising printed circuit boards, IC packages, connectors and IC sockets. The automated flows reduce time-consuming manual setup and errors, and streamline the generation of system pass/fail metrics and system verification. This workflow is the foundation of the CPS solution, as it integrates IC models with package and printed circuit board simulation.

In ANSYS 18, we introduce a unique layout assembly capability that supports multiple IC packages, printed circuit boards and connectors in a single simulation. We’re advancing this capability by bringing transient circuit-based simulation directly into the layout, allowing engineers to perform system-level verification. We also extended ECAD-MCAD meshing efficiency and robustness, along with integration of simulation capabilities, into the HFSS 3-D Layout design flow.

Some of the most common challenges in performing complex system simulations are data sharing with IP protection, simulating large 3-D models and creating a schematic to wire models from different field solvers to better predict system time- and frequency-domain performance. All of these challenges are resolved via ANSYS 3-D Layout Assembly with ANSYS 3-D Components. ANSYS 3-D Components are self-contained HFSS models which may contain assemblies of model geometry, excitations, boundary conditions and parametric variables;  their IP is protected by encryption. Using 3-D Layout with integrated HFSS provides a layout assembly approach for connecting PCBs, ICs and arbitrary 3-D components.

With our new release, ANSYS HFSS 3-D Layout breaks the barrier between 3-D geometry and electrical layout geometry. Users can now simulate a complete system such as a laptop with CAD integration of connectors, modeled in 3-D, on a printed circuit board electrical layout. Complete system analysis using the Nexxim transient circuit engine and frequency domain field solver simulations from HFSS and SIwave, with their integrated driver and receiver models, can then be performed using an HFSS 3-D Layout assembly.

Maybe the biggest barrier in today’s high-speed digital designs is the effect of temperature. As power density within digital electronics products continues to increase, the ability to accurately predict electrothermal effects becomes paramount. Bridging the gap between the mechanical domain and the electrical domain requires a design flow that reduces learning time and can be easily adopted by industry.

ANSYS 18 delivers a CAD first approach to easily and accurately predict electrothermal results for both MCAD and ECAD geometries. We’re breaking the silos between electrical and mechanical engineering. Reliable electronics must meet requirements in both domains. ANSYS 18 can extract layers with a unique metal fraction mapping algorithm to automatically set up package/board designs for mechanical analysis.

For the first time, a design flow exists that can perform DC analysis, map Joule heating to a mechanical solver, and then produce temperature profiles with associated mechanical deformation and stress. It’s a chip-package-board solution that allows engineers to evaluate electrical, thermal and structural behavior. Reducing design time while improving accuracy has a significant impact on digital electronic products.

With ANSYS 18, signal integrity simulation has been turned inside out with electromagnetic field simulation. Instead of solving the circuits first and the electromagnetic physics later — the way it used to be done — modern simulation has placed physics-based solvers in the foreground, supported by circuit and system simulation.

Electromagnetic simulation of entire electronic systems can now be performed from a layout assembly. Advanced numerical methods, high-performance computing, new technologies for handling massive EDA data in an automated way, and multiphysics for determining thermal and stress effects have combined to make this powerful, advanced electronic design methodology possible. The barriers between IC, mechanical, thermal and electrical design have been significantly reduced.

ansys webinarsDo you want to learn more about how ANSYS 18 has enhanced the Chip-Package-System workflow to address design challenges in power integrity, signal integrity, ESD, thermal and structural challenges? Discover how you can break down barriers in your own design flow. Join me on February 23rd when I will present an overview of the ANSYS 18 signal and power integrity suite during a 50-minute webinar. I look forward to discussing our advancements in simulation for high-speed digital design with you.