Modern high-tech products using chips that are designed with the latest deep sub-micron process technologies (28nm and below) and FinFET technology offer higher performance, smaller footprint and lower power. However, power integrity analysis and reliability challenges become increasingly complex for chip package designs using these devices.
More stringent manufacturing rules present basic layout challenges and new design innovations require careful consideration of effects such as electromigration (EM), electrostatic discharge (ESD) and noise coupling through substrate, signal and power rails. Even the most thorough sign-off process can often fail to prevent tape-out hurdles or extensive redesign. Therefore, forward-thinking design teams need to address reliability and power integrity long before final sign-off, accounting for their impact during the design process itself.
Sign-off checks throughout the design process
As designs incorporate an increased number of voltage domains, clocks, activity profiles and power management schemes in denser layouts, it becomes difficult to correlate changes in architectural decisions to power integrity and reliability issues without properly assessing the effects at various stages of the design. A staged approach also reveals potential cost-cutting opportunities along the way, such as customizing the power grid or the number of components like power gates, high-VT cells or decaps, to meet specifications that can prevent over-design.
Design teams find ways to reduce power before any physical implementation takes place by performing power estimation and optimization at the architectural phase, using the RTL design. Using these power estimates to perform early analysis of the chip or blocks that comprise the chip, designers can determine potential power integrity and reliability concerns in the physical implementation. Identifying gross violations and power planning mishaps early on saves headaches later. As progress is made on different aspects of the design — such as finalizing specific power grid topologies and power gate sizes/placements, deciding on a package design, and determining activity factors/vectors of various blocks — the design is re-evaluated at every step for transient power noise effects, EM and ESD robustness.
By leveraging the accuracy and versatility of ANSYS IC sign-off tools from early physical design planning to sign-off, design teams are able to:
- See the direct impact that various incremental design decisions play on their ultimate chip performance.
- Correct for undesired effects as each significant change is introduced.
- Be aware of excessive over- or under-design that may have greater business implications down the road.
A good example of benefits derived from incremental analysis is the recent trend of co-designing the chip with the package, where effects on the die and the package are simultaneously analyzed to see where bottlenecks might occur as both designs evolve. Subsequent design decisions are made based on how either or both can be altered to provide optimal performance. The one-size-fits-all package is becoming a thing of the past as greater customization for both the die and the package can account for detrimental L(di/dt) or RC parasitic effects. With recent tool advancements such as ANSYS RedHawk-CPA, die designers can observe IR effects on the imported package layout itself and provide valuable feedback to the package team for potential areas of improvement.
Anyone taking the bold next step into FinFET or tri-gate technologies must account for increased thermal effects. In addition, EM limits are up to 30 percent more stringent, making standalone EM analysis on sub-blocks (standard cells and IPs) using sign-off tools prior to a full-chip analysis even more critical so that problems can be better isolated and resolved. Though simple metal width adjustments may have worked in the past for small EM violations, teams now face the prospect of non-trivial architectural or physical redesign due to unforeseen effects such as a large current inrush caused by bad switch placement or sensitive timing paths impacted by dynamic voltage drop.
To avoid costly and time-consuming iterations of parts of (or the whole) design due to significant issues at the final sign-off stage, it is wise to use a sign-off tool throughout the various stages of the design cycle. Doing so will provide the accuracy needed to efficiently drive a design to completion and achieve post-silicon success. Running a sign-off tool once at the end of a design cycle may result in unexpected and unsatisfactory results. To be confident before final sign-off, power integrity and reliability effects need to be accounted for as the design evolves from start to finish.
These types of a paradigm shifts in analysis techniques to meet new demands is nothing new. Electrical engineers cannot ignore influential new physics because they were not relevant in the past, and should take proactive steps to counter their unwanted effects.
To learn more about ANSYS RedHawk, watch this webinar about how to use RedHawk 2014 for Power Noise and Reliability Sign-off of FinFET Based Designs or visit the RedHawk Release Highlights webpage.