Today, I’m pleased to announce the launch of ANSYS Redhawk 2014. RedHawk was the industry’s first foundry-certified, full-chip sign-off solution for power noise and reliability. Over the past 10 years, its accuracy, performance and scalability benefits have enabled thousands of successful designs to make it into production by all major semiconductor companies. The newest version of the software will help to ensure that RedHawk continues to be a technology leader and solution of choice for chip designers around the world.
As semiconductor technology evolves into advanced manufacturing processes that leverage smaller and smaller sizes, ANSYS RedHawk 2014 expands on its existing capabilities to address the emerging needs arising from the use of FinFET (three-dimensional transistor) structures. The use of FinFET transistors is resulting in a monumental shift in the semiconductor industry as designers take advantage of the device’s ability to deliver lower-power higher-performance chips, allowing companies to stay competitive in fast-growing electronics market segments such as mobile, automotive and the Internet of Things (IoT).
The number-one priority for any simulation solution is sign-off accuracy. Without it, designers cannot rely on the tool to provide correct results. This becomes even more important when the tolerance for error reduces by 50% or more. As designs migrate to smaller process nodes with complex structures, more factors contribute to the generation of power noise. At the same time, the supply voltage for advanced designs is lower, resulting in a smaller noise margin. Designs implemented using sub-20 nm processes have higher device counts and higher power density, compared to the previous generation. Furthermore, the power delivery network (PDN) can have issues inside the chip, in the package or on the board. So the entire chip-package-board needs to be simulated holistically. All these factors make sign-off quality power integrity analysis a major challenge.
ANSYS RedHawk 2014 includes several new capabilities, as well as software architectural improvements and flow optimizations, to address such challenges.
The newest release offers distributed machine processing (DMP), which enables the analysis of 100 M+ instances or 2 B+ node designs by significantly reducing the total turn-around time while maintaining its silicon-validated sign-off accuracy. It effectively distributes a large design database across several machines and simulates each partition in the context of the entire chip, including package and PCB. This unique in-context analysis methodology enables RedHawk 2014 to reduce memory usage and run-time by two to three times. Unlike hierarchical methods that cannot model time-varying current flow across the block boundaries, RedHawk’s DMP capability delivers sign-off accurate full-chip voltage drop, EM and ESD analyses.
Sign-off quality voltage drop analysis demands the inclusion of accurate and representative IP models and package/PCB parasitics. So the latest release introduces RedHawk-CPA, the industry’s first chip-package co-analysis solution. It enables native chip-package co-analysis by bringing in both chip and package layouts into the same simulation platform, providing immediate feedback regarding the impact of on-chip current distribution — over time and over chip area — on the package design, as well as the impact of the package parasitics on the chip’s performance.
FinFET architecture does more than reduce the noise margin: It increases local self-heating, which worsens reliability issues such as electromigration (EM) and electrostatic discharge (ESD). RedHawk 2014 accurately analyzes EM violations for power/ground and signal line, while minimizing false positives. Its proprietary current-flow aware extraction techniques help to achieve sign-off quality results for every wire and via in a design. ANSYS PathFinder, which is part of the RedHawk platform, supports IP to SoC-level ESD integrity analysis by providing both connectivity and interconnect failure checks for all current flow pathways (wires and vias) from an ESD event (HBM or CDM).
The ANSYS power noise and reliability ecosystem extends beyond the RedHawk simulation platform to include production-proven system-level simulation solutions, empowering designers with system-aware chip simulation and chip-package-aware system simulation methodologies to ensure that the chip and the system are designed to work together at the lowest cost.
For more information, check out the benefits at RedHawk 2014. And if you’re attending the Design Automation Conference (DAC) this year, I’d like to invite you to attend a SKY Talks that I’ve been invited to present on Tuesday, June 3rd, at 11:30 am. I’ll be discussing Managing Multi-Scale, Multi-Physics Challenges in the New Generation of Automotive Systems and the challenges arising from expanding consumer needs and the myriad of regulatory requirements, and reviewing the opportunities from exploring multiple ‘what-if’ scenarios leading to optimal design.