As designs increase in complexity to cater to the insatiable need for more compute power spurred by different AI applications ranging from data centers to self-driving cars, designers are constantly faced with the challenge of meeting the elusive PPA (Power Performance and Area) targets.
PPA over-design has repercussions resulting in increased product cost as well as potential missed schedules with no guarantee of product success. Advanced SoCs pack more functionality and performance which result in higher power density. Traditional approaches of uniformly over-designing the power grid which has worked in the past is no longer an option with routing resources becoming severely constrained. To add to these woes, there are hundreds of combinations of PVT corners to solve for along with the increasing number of applications. Continue reading →
Every new, smaller technology node developed in the semiconductor field has its own challenges, and the 7nm node is no exception. Usually a smaller technology node decreases price per transistor, but the cost benefits usually obtained from the smaller geometry are not as significant as in previous node changes. In fact, the increased complexity of lithography masks has made the unit cost per transistor slightly higher for 7nm devices. To offset these higher costs, products using 7nm semiconductors need higher margins, larger sales volumes and significantly higher performance than previous nodes. Achieving these goals requires designers to overcome a number of technical challenges, making upfront engineering simulation even more important than ever.
In June, I attended the Design Automation Conference in Austin, TX and LiveWorx in Boston, MA. I would like to share some key observations from both events.
The Internet of Things is going to be big; very big!
Success requires partnerships.
IoT is about monetizing data.
Engineering simulation is essential.
The Internet of Things is going to be big!
At the just concluded Design Automation Conference in Austin, speaker after speaker stressed this.
Silicon Labs CEO, Tyson Tuttle, noted that there will be 70 billion Internet connected devices by 2025 with accompanying semiconductors to power them. He repeated McKinsey’s forecast the the Internet of Things will drive between $4 -11 trillion in global economic impact by 2025. Continue reading →
For engineers designing integrated circuits (IC) including system on chips (SoC), using integration and miniaturization to increase performance and bandwidth while reducing power and footprint has been an ongoing, continuous strategy. Now TSMC has developed an InFO packaging technology that is truly a game changer!
Why is InFO technology a game changer?
As mobile phones and other handheld devices continue to be a key driver of semiconductor innovation, chips often go into systems that demand a small footprint and minimum height. Since wiring dimensions of a chip are much smaller than that on a board, a chip cannot be mounted directly on a board. Continue reading →
The internet has inspired the growth and permeation of electronics into everything from coffee machines to automobiles, hand‐held devices, mobile smart phones, healthcare monitoring and treatment equipment, communication devices, high‐end servers and more. Most of these are “always on,” and require the systems on chip (SoC) that drive the electronics to be: Continue reading →
This year, ANSYS received yet another TSMC’s Partner of the Year Award in the category of joint development of the 10nm FinFET Design Infrastructure. It has been 11 years since TSMC adopted ANSYS RedHawk as an integral part of its Reference Flow 5.0 in 2004, and that was the industry’s first reference flow to achieve dynamic power noise closure for nanometer designs.
Through longstanding, close collaboration between TSMC and ANSYS, ANSYS RedHawk and ANSYS Totem have always been enabled as power integrity and reliability solutions for the most advanced process technology. This has played and continues to play a critical role, enabling mutual customers to innovate and creating revolutionary electronic devices — for smart phones, high-performance computing, automotive, and wearable applications. Continue reading →
Modern high-tech products using chips that are designed with the latest deep sub-micron process technologies (28nm and below) and FinFET technology offer higher performance, smaller footprint and lower power. However, power integrity analysis and reliability challenges become increasingly complex for chip package designs using these devices.
More stringent manufacturing rules present basic layout challenges and new design innovations require careful consideration of effects such as electromigration (EM), electrostatic discharge (ESD) and noise coupling through substrate, signal and power rails. Even the most thorough sign-off process can often fail to prevent tape-out hurdles or extensive redesign. Therefore, forward-thinking design teams need to address reliability and power integrity long before final sign-off, accounting for their impact during the design process itself. Continue reading →