ANSYS Chip Package System Analysis Ready for the “Next Big Thing” in Mobile Design

Delivering a truly innovative product for the mobile revolution requires optimization at every level of design for power, performance, thermal and structural integrity. The success of today’s electronic products are tied to the success of their entire system, including all components from antenna to board, and from chip to chassis. Designing a smart watch, for example, requires multiple iterations of chip, package, board, antenna, and cooling strategy to arrive at a final optimized product. Continue reading

Achieving Power Noise Closure and Reliability Sign-off Accuracy for SoCs using Advanced Process Technologies

TSMC’s Partner of the Year Award

TSMC’s Partner of the Year Award

This year, ANSYS received yet another TSMC’s Partner of the Year Award in the category of joint development of the 10nm FinFET Design Infrastructure.  It has been 11 years since TSMC adopted ANSYS RedHawk as an integral part of its Reference Flow 5.0 in 2004, and that was the industry’s first reference flow to achieve dynamic power noise closure for nanometer designs.

Through longstanding, close collaboration between TSMC and ANSYS, ANSYS RedHawk and ANSYS Totem have always been enabled as power integrity and reliability solutions for the most advanced process technology. This has played and continues to play a critical role, enabling mutual customers to innovate and creating revolutionary electronic devices — for smart phones, high-performance computing, automotive, and wearable applications. Continue reading