Leaping the Chasm to 7nm Semiconductor Design

Every new, smaller technology node developed in the semiconductor field has its own challenges, and the 7nm node is no exception. Usually a smaller technology node decreases price per transistor, but the cost benefits usually obtained from the smaller geometry are not as significant as in previous node changes. In fact, the increased complexity of lithography masks has made the unit cost per transistor slightly higher for 7nm devices. To offset these higher costs, products using 7nm semiconductors need higher margins, larger sales volumes and significantly higher performance than previous nodes. Achieving these goals requires designers to overcome a number of technical challenges, making upfront engineering simulation even more important than ever.7nm semiconductor design challenges

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Tackling Next Generation CPS Design Challenges

System design and even system integration have taken on a whole new meaning with the latest trends in mobile and wearable computing. Integrating the compute power formerly associated with super-computers into a wrist band puts entirely new challenges on engineers, as they struggle with ensuring  signal and power integrity, as well as controlling the thermal profile. For these next-generation designs, full system analysis in the form of a Chip-Package-System (CPS) co-analysis is not an option anymore — it is an absolute necessity in order to achieve convergence. Continue reading

Chip-Package-System Design Approach

image showing chip-package-systemSince ANSYS acquired Apache Design last year, our team has been developing a chip-package-system (CPS) design approach that provides engineers with enough knowledge and confidence to make optimal cost, performance and reliability decisions for their designs.

Our simulation-driven CPS methodologies make it possible to provide the entire electronics supply chain with a more robust and reliable design that has greater predictability. This simulation flow enables engineers to resolve many or their toughest design challenges. The solution provides fully coupled chip-aware, physics-aware simulations for the chip-package-system design. The best-in-class dynamic power extraction solution from Apache Design is now coupled to industry-standard physical extraction simulators from ANSYS, providing full electromagnetic extraction, signal and power integrity, and electromagnetic interference analysis, as well as thermal, mechanical stress and other solutions needed as 3-D integrated circuit technologies become mainstream. Continue reading