System design and even system integration have taken on a whole new meaning with the latest trends in mobile and wearable computing. Integrating the compute power formerly associated with super-computers into a wrist band puts entirely new challenges on engineers, as they struggle with ensuring signal and power integrity, as well as controlling the thermal profile. For these next-generation designs, full system analysis in the form of a Chip-Package-System (CPS) co-analysis is not an option anymore — it is an absolute necessity in order to achieve convergence. Continue reading
Modern high-tech products using chips that are designed with the latest deep sub-micron process technologies (28nm and below) and FinFET technology offer higher performance, smaller footprint and lower power. However, power integrity analysis and reliability challenges become increasingly complex for chip package designs using these devices.
More stringent manufacturing rules present basic layout challenges and new design innovations require careful consideration of effects such as electromigration (EM), electrostatic discharge (ESD) and noise coupling through substrate, signal and power rails. Even the most thorough sign-off process can often fail to prevent tape-out hurdles or extensive redesign. Therefore, forward-thinking design teams need to address reliability and power integrity long before final sign-off, accounting for their impact during the design process itself. Continue reading