Chip-Package-System Workflow Breaks Down the Barriers in Electronics Design

Chip-Package-System Workflow Engineers are challenged to design modern electronic systems that operate at higher speeds with lower power with ever greater functionality in an ever shrinking footprint. These design challenges drive engineers to perform Chip-Package-System (CPS) co-design and analysis. However, the design flow is often unconnected, and design data is exchanged manually leading to slow design times and error prone design methodologies. ANSYS 18 breaks down the barriers between simulation domains and delivers a Chip-Package-System workflow that enables engineers to accomplish their work in a rapid and convenient way. Continue reading

ANSYS Chip Package System Analysis Ready for the “Next Big Thing” in Mobile Design

Delivering a truly innovative product for the mobile revolution requires optimization at every level of design for power, performance, thermal and structural integrity. The success of today’s electronic products are tied to the success of their entire system, including all components from antenna to board, and from chip to chassis. Designing a smart watch, for example, requires multiple iterations of chip, package, board, antenna, and cooling strategy to arrive at a final optimized product. Continue reading

Designing without Borders – DesignCon 2016

designcon demosProduct development of today’s complex mobile and IoT devices requires the cooperation of independent design teams working at the chip, package, and system level. However, several roadblocks in the electronics design flow make this cooperation very difficult, impacting time, effort, and ultimately the cost required to deliver a successful product to market. Continue reading

ANSYS 16.0 ‘What’s New’ Webinars Schedule

ansys how to videos youtubeWith the release of ANSYS 16.0 last week, we know that you may be looking for more detail around “What’s New”. Our team of experts have put together a series of webinars over the coming weeks that will take a deeper dive into the enhancements you’ll see.

Register today for the webinar(s) that spark your interest. Continue reading

Tackling Next Generation CPS Design Challenges

System design and even system integration have taken on a whole new meaning with the latest trends in mobile and wearable computing. Integrating the compute power formerly associated with super-computers into a wrist band puts entirely new challenges on engineers, as they struggle with ensuring  signal and power integrity, as well as controlling the thermal profile. For these next-generation designs, full system analysis in the form of a Chip-Package-System (CPS) co-analysis is not an option anymore — it is an absolute necessity in order to achieve convergence. Continue reading

Enabling EMI Clean Design: Starting with PCB SI & PI Analysis

With the trend to more high-performance and compact systems, EMI compliance has become a critical metric for system success in the automotive, computing, and aerospace industries. Electromagnetic interference issues discovered late in the design cycle can result in the entire system failing to meet regulatory EMI/EMC requirements. Addressing regulatory compliance and product debug can cost not only engineering time to investigate and mitigate issues, but can also threaten product release dates. PCB designers, therefore, need a strategy to address potential issues early in their design, to ensure the system meets compliance. Continue reading

How Is FinFET Technology Changing the Meaning of Chip Sign-Off?

Physical Representation FinFET TechnologyModern high-tech products using chips that are designed with the latest deep sub-micron process technologies (28nm and below) and FinFET technology offer higher performance, smaller footprint and lower power. However, power integrity analysis and reliability challenges become increasingly complex for chip package designs using these devices.

More stringent manufacturing rules present basic layout challenges and new design innovations require careful consideration of effects such as electromigration (EM), electrostatic discharge (ESD) and noise coupling through substrate, signal and power rails. Even the most thorough sign-off process can often fail to prevent tape-out hurdles or extensive redesign. Therefore, forward-thinking design teams need to address reliability and power integrity long before final sign-off, accounting for their impact during the design process itself. Continue reading

RedHawk 2014 Enables FinFET-Based Designs

image of ANSYS RedHawk GUIToday, I’m pleased to announce the launch of ANSYS Redhawk 2014. RedHawk was the industry’s first foundry-certified, full-chip sign-off solution for power noise and reliability. Over the past 10 years, its accuracy, performance and scalability benefits have enabled thousands of successful designs to make it into production by all major semiconductor companies. The newest version of the software will help to ensure that RedHawk continues to be a technology leader and solution of choice for chip designers around the world. Continue reading

What’s With All The Noise About FinFETs?

Power noise integrity challenges designers face in FinFET-based design

ReFinFET2cently, there has been a lot of talk around designing systems-on-chips (SoCs) using FinFET technology. So what is a FinFET and what’s all the noise about? Simply put, FinFET is a three-dimensional field-effect transistor (FET) where the gate is wrapped around an elevated channel, creating a “fin”. Compared to traditional planar MOS transistors, FinFET architecture offers reduced leakage power and increased drive current, resulting in lower power, higher performance SoCs for mobile, networking, computing, and other applications. Continue reading