Engineers are challenged to design modern electronic systems that operate at higher speeds with lower power with ever greater functionality in an ever shrinking footprint. These design challenges drive engineers to perform Chip-Package-System (CPS) co-design and analysis. However, the design flow is often unconnected, and design data is exchanged manually leading to slow design times and error prone design methodologies. ANSYS 18 breaks down the barriers between simulation domains and delivers a Chip-Package-System workflow that enables engineers to accomplish their work in a rapid and convenient way. Continue reading
Delivering a truly innovative product for the mobile revolution requires optimization at every level of design for power, performance, thermal and structural integrity. The success of today’s electronic products are tied to the success of their entire system, including all components from antenna to board, and from chip to chassis. Designing a smart watch, for example, requires multiple iterations of chip, package, board, antenna, and cooling strategy to arrive at a final optimized product. Continue reading
Product development of today’s complex mobile and IoT devices requires the cooperation of independent design teams working at the chip, package, and system level. However, several roadblocks in the electronics design flow make this cooperation very difficult, impacting time, effort, and ultimately the cost required to deliver a successful product to market. Continue reading
With the release of ANSYS 16.0 last week, we know that you may be looking for more detail around “What’s New”. Our team of experts have put together a series of webinars over the coming weeks that will take a deeper dive into the enhancements you’ll see.
Register today for the webinar(s) that spark your interest. Continue reading
System design and even system integration have taken on a whole new meaning with the latest trends in mobile and wearable computing. Integrating the compute power formerly associated with super-computers into a wrist band puts entirely new challenges on engineers, as they struggle with ensuring signal and power integrity, as well as controlling the thermal profile. For these next-generation designs, full system analysis in the form of a Chip-Package-System (CPS) co-analysis is not an option anymore — it is an absolute necessity in order to achieve convergence. Continue reading
With the trend to more high-performance and compact systems, EMI compliance has become a critical metric for system success in the automotive, computing, and aerospace industries. Electromagnetic interference issues discovered late in the design cycle can result in the entire system failing to meet regulatory EMI/EMC requirements. Addressing regulatory compliance and product debug can cost not only engineering time to investigate and mitigate issues, but can also threaten product release dates. PCB designers, therefore, need a strategy to address potential issues early in their design, to ensure the system meets compliance. Continue reading
Today, we announced that our ANSYS HFSS users can reduce design time and cost, while optimizing complete electronic system performance, thanks to linear circuit simulation embedded within the latest version of this software.
At a high level, a more streamlined simulation workflow enables engineers to focus on enhancing complete system reliability and signal quality as well as analyzing electromagnetic interference. New HFSS product options for radio frequency (RF) and signal integrity (SI) analyses are also available — making high-frequency (HF) and high-speed electronic device design even more comprehensive. Continue reading