High-Capacity Power Signoff Using Big Data

As designs increase in complexity to cater to the insatiable need for more compute power spurred by different AI applications ranging from data centers to self-driving cars, designers are constantly faced with the challenge of meeting the elusive PPA (Power Performance and Area) targets.

PPA over-design has repercussions resulting in increased product cost as well as potential missed schedules with no guarantee of product success. Advanced SoCs pack more functionality and performance which result in higher power density. Traditional approaches of uniformly over-designing the power grid which has worked in the past is no longer an option with routing resources becoming severely constrained. To add to these woes, there are hundreds of combinations of PVT corners to solve for along with the increasing number of applications.  Continue reading

Design of Advanced Driver Assistance Systems – A CPS Approach

An automobile is the biggest and most complex connected device used by consumers today. Advanced driver assistance systems (ADAS) is one of the fastest growing automotive applications. Stringent government requirements on automotive safety, fuel consumption and technology-focused consumer preferences are fueling the growth of ADAS. Driven primarily by safety, ADAS capabilities were first implemented in premium vehicles as key differentiators to enhance the user experience and protect the vehicle and its occupants. It started with features like parking assistance, adaptive breaking systems (ABS), adaptive cruise control and tire pressure monitoring. Continue reading

Introducing ANSYS SeaScape for Chip Simulation

seahawk seascapeDue to the volumes of data that need to be analyzed and the limits in simulation tool capabilities and processing power, sign-off in chip and electronic system design has traditionally followed a monolithic, margin-based approach that has resulted in larger die-size and longer development times. Today I’d like to tell you about a fundamentally new approach and software architecture called ANSYS SeaScape that will revolutionize chip simulation by harnessing the power of elastic computing, machine learning and big data to perform multiphysics simulations and design more compact, complex chips. This approach has demonstrated its ability speed up chip design and help eliminate many of the inefficiencies of traditional methodologies. Continue reading

10X Gain in Productivity of Chip‐level Power Integrity Analysis

The internet has inspired the growth and permeation of electronics into everything from coffee machines to automobiles, hand‐held devices, mobile smart phones, healthcare monitoring and treatment equipment, communication devices, high‐end servers and more. Most of these are “always on,” and require the systems on chip (SoC) that drive the electronics to be: Continue reading

Achieving Power Noise Closure and Reliability Sign-off Accuracy for SoCs using Advanced Process Technologies

TSMC’s Partner of the Year Award

TSMC’s Partner of the Year Award

This year, ANSYS received yet another TSMC’s Partner of the Year Award in the category of joint development of the 10nm FinFET Design Infrastructure.  It has been 11 years since TSMC adopted ANSYS RedHawk as an integral part of its Reference Flow 5.0 in 2004, and that was the industry’s first reference flow to achieve dynamic power noise closure for nanometer designs.

Through longstanding, close collaboration between TSMC and ANSYS, ANSYS RedHawk and ANSYS Totem have always been enabled as power integrity and reliability solutions for the most advanced process technology. This has played and continues to play a critical role, enabling mutual customers to innovate and creating revolutionary electronic devices — for smart phones, high-performance computing, automotive, and wearable applications. Continue reading