High-Capacity Power Signoff Using Big Data

As designs increase in complexity to cater to the insatiable need for more compute power spurred by different AI applications ranging from data centers to self-driving cars, designers are constantly faced with the challenge of meeting the elusive PPA (Power Performance and Area) targets.

PPA over-design has repercussions resulting in increased product cost as well as potential missed schedules with no guarantee of product success. Advanced SoCs pack more functionality and performance which result in higher power density. Traditional approaches of uniformly over-designing the power grid which has worked in the past is no longer an option with routing resources becoming severely constrained. To add to these woes, there are hundreds of combinations of PVT corners to solve for along with the increasing number of applications.  Continue reading

Achieving Power Noise Closure and Reliability Sign-off Accuracy for SoCs using Advanced Process Technologies

TSMC’s Partner of the Year Award

TSMC’s Partner of the Year Award

This year, ANSYS received yet another TSMC’s Partner of the Year Award in the category of joint development of the 10nm FinFET Design Infrastructure.  It has been 11 years since TSMC adopted ANSYS RedHawk as an integral part of its Reference Flow 5.0 in 2004, and that was the industry’s first reference flow to achieve dynamic power noise closure for nanometer designs.

Through longstanding, close collaboration between TSMC and ANSYS, ANSYS RedHawk and ANSYS Totem have always been enabled as power integrity and reliability solutions for the most advanced process technology. This has played and continues to play a critical role, enabling mutual customers to innovate and creating revolutionary electronic devices — for smart phones, high-performance computing, automotive, and wearable applications. Continue reading