Creating Reliable SoC Designs Using N7 and InFO-WLP Technologies

According to Gartner, designing, testing and manufacturing 7nm FinFET-based system on a chip (SoC) requires massive resources: as much as $270 million and 500 man-years to bring the chip to market. Encapsulating such chips within a 2.5/3D package such as InFO-WLP improves power, performance and form factor while increasing the cost of design. To make a profit on that level of investment, the market for these chips tend to be high-end mobile and enterprise applications. To satisfy customer needs in these demanding markets, design teams have to deliver highly integrated devices that operate seamlessly and reliably for long periods of time. Additionally, you have to reduce the engineering time and cost, and ensure “first-time” working silicon. To do this you will need to move away from the traditional silo-based design flow to a chip-package-board co-simulation workflow and methodology. Continue reading

Achieving Power Noise Closure and Reliability Sign-off Accuracy for SoCs using Advanced Process Technologies

TSMC’s Partner of the Year Award

TSMC’s Partner of the Year Award

This year, ANSYS received yet another TSMC’s Partner of the Year Award in the category of joint development of the 10nm FinFET Design Infrastructure.  It has been 11 years since TSMC adopted ANSYS RedHawk as an integral part of its Reference Flow 5.0 in 2004, and that was the industry’s first reference flow to achieve dynamic power noise closure for nanometer designs.

Through longstanding, close collaboration between TSMC and ANSYS, ANSYS RedHawk and ANSYS Totem have always been enabled as power integrity and reliability solutions for the most advanced process technology. This has played and continues to play a critical role, enabling mutual customers to innovate and creating revolutionary electronic devices — for smart phones, high-performance computing, automotive, and wearable applications. Continue reading